Advance Discount Deadline October 5th! |
| CALL FOR PARTICIPATION |
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| The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.
Workshop Program – The workshop program contains the following elements.
- Keynote address: “3D Integration: TSV and the Impact on DfT” by Stephane Lecomte, Member of Test Engineering Technical Staff at ST-Ericsson.
- Invited Address: “3D-Driven System Design – Present and Future”
by Paul Franzon, Professor, North-Carolina State University.
- Five sessions with in total 14 paper presentations.
- Continuous display of posters and table-top demos.
- A panel discussion with market analysts, editors, and bloggers
on “The 3D Buzz: Hype versus Reality”.
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| Key Dates |
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| Advance Discount Registration Deadline: October 5, 2012! |
| Workshop Registration |
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Participation – You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as far as made available by their presenters), workshop reception, continental breakfast, lunch, and break refreshments. On-line registration is available via the workshop’s website (http://3dtest.tttc-events.org). Alternatively, register on-site during Test Week at the ITC Registration Counter at the Disneyland Hotel; admission for on-site registrants is subject to availability. Early (= discount) registration expires October 5, 2012! |
| Advance Program |
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Thursday -- Friday
November 8, 2012 (Thursday) |
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| 16:00h |
OPENING SESSION |
16:00h |
Welcome Address
General Chair: Yervant Zorian – Synopsys, USA
Program Introduction
Program Chairs: Erik Jan Marinissen – IMEC, BE
Said Hamdioui – TU Delft, NL |
16:15h |
Keynote Address: 3D Integration: TSV and the Impact on DfT
Stephane Lecomte – ST-Ericsson, FR
3D die-to-die stacking has received a lot of attention recently, as it opens the door to integration of heterogeneous technologies. Among the first challenges were the set-up of a reliable Through-Silicon Via (TSV) technology module, and efficient die stacking and manufacturing processes. Design-for-Test (DfT) requirements had to evolve, to address new challenges as TSVs, top-die access, and die-to-die interconnect coverage. This talk discusses how innovative these new DfT solutions really need to be, in view of short-term 3D applications. We review a few 3D examples made by Leti and ST-Ericsson and their potential future applications in the smart-phone market. |
16:45h |
Invited Address: 3D-Driven System Design – Present and Future
Paul Franzon – NCSU, USA
After years of research and development, Through-Silicon Vias (TSVs) are becoming a manufacturing reality. Soon, a wave a new TSV-based 3D stacked ICs (and “2½D”-stacked ICs) will hit the market, including CMOS image sensors, memory cubes, stacked FPGAs, and memory-on-logic. This will be followed by a set of more sophisticated products likely to have a focus on heterogeneous integration. For digital systems, one particularly benefit for going into the third dimension is reduced power consumption. However, to justify the investment it must be possible to achieve power savings of 25% or more. This cannot be achieved solely through shorter wires! 3D-specific design solutions are needed. A particular complexity in 3D integration is that designs that might be assembled into a 3D stack are likely to be designed at different times and places. This creates the need for common interface IP and interchange standards. The requirements and progress towards these will be presented and discussed. |
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| 17:15h |
Session 2 - 3D Design-for-Test |
17:15 |
Design for Testing 3D-TSVs Connecting Logic Die and Memory Die
Jing Ye, Yu Hu, Xiaowei Li – Chinese Academy of Sciences, CN; Ruifeng Guo, Wu-Tung Cheng, Yu Huang, Liyang Lai – Mentor Graphics, USA |
17:40 |
Post-Test Insertion Retiming for TSV Boundary Cell in 3D ICs
Brandon Noia, Krishnendu Chakrabarty – Duke University, USA |
18:05 |
A Low-Overhead Method for Pre-Bond Test of Resonant 3-D Clock Distribution Networks
Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Michele – EPFL, CH |
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| 18:30 - 19:00h |
Session 3 - Posters and Demos |
Poster 1 |
Optimization of MEMS-IC SiP Development Reliable Design Methods
Grzegorz Janczyk, Tomasz Bieniek – Instytut Technologii Elektronowej, PL |
Poster 2 |
Standardization Working Group on 3D-Test / Project P1838
Erik Jan Marinissen – IMEC, BE; Adam Cron – Synopsys, USA |
Poster 3 |
New Adaptive Ion Milling Technology (AIM) Enables Accurate and Fast Analysis for a Wide Variety of Applications
Vladimir Zheleznyak, Dima Gobuslavsky – Camtek, IL |
Poster 4 |
Reliability Investigation by Examination of Dedicated MEMS/ASIC and NW’s Test Sturctures Related to Novel 3D SiP and Nano-Sensors Systems
Tomasz Bieniek, Grzegorz Janczyk - Instytut Technologii Elektronowej, PL |
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| 19:00h Workshop Reception |
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November 9, 2012 (Friday) |
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| 09:15h |
Session 5 - 3D Electronic Design Automation |
09:15 |
Extension of a 3D-DfT Architecture for Embedded Cores and Multiple Towers
Brion Keller, Christos Papameletis, Vivek Chickermane – Cadence Design Systems, USA; Erik Jan Marinissen – IMEC, BE |
09:40 |
An EDA Approach to 3D-IC DfT Requirements
Etienne Racine, Ron Press, Rick Fisette, Martin Keim – Mentor Graphics, USA |
10:05 |
An Effective Infrastructure IP for Memory Dies in 3D-ICs
Yervant Zorian, Gurgen Harutunyan – Synopsys, USA |
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| 10:30 - 10:45h |
Session 6 - Posters and Demos |
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Coffee & Tea Provided |
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| 10:45h |
Session 7 - Editor’s Panel Discussion
Moderator: Françoise von Trapp – « Queen of 3D », Founder/Director 3D Incites, USA |
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The 3D Buzz: Hype versus Reality
Panelists:
Ira Feldman – Principal Consultant, Feldman Engineering Corp., USA
Herb Reiter – President, eda2asic, USA
Jan Vardaman – CEO, TechSearch International, Inc., USA
Paul Werbaneth – Executive Consultant, Semiconductor Technologies, USA
You’ve read their market reports and columns, attended their presentations, subscribed to their blogs, and followed them on LinkedIn and Twitter. They may not be the ones making the manufacturing decisions about when to implement 3D technologies, but they’ve certainly done their part in influencing key decision makers in semiconductor device manufacturing, guiding them on path to 2.5D and 3D ICs through their analysis, research, words and observations. They are the analysts and journalist/bloggers who have been following different aspects of the 3D story for years. We’ve gathered four of them to share their perspective on what’s hype and what’s really in the march towards commercialization of 3D ICs.
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| 12:00 - 13:00h Workshop Luncheon |
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| 13:00 - 13:20h |
Session 8 - Posters and Demos |
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| 0:00 AM
- 0:00 AM |
Session 9 - 3D Cost Modelling and Yield
Chair: First Last (Affiliation) |
13:20 |
The Implications of Fault Toleration for Yield, Known Good Die, and Test Strategies in 3D Integration
Kenneth Rose, Adam Beece, Tong Zhang, James Lu – Rensselaer Polytechnic Institute, USA |
13:55 |
3D-COSTAR: A Cost Model For 3D Stacked ICs
Mottaqiallah Taouil, Said Hamdioui – TU Delft, NL;
Erik Jan Marinissen – IMEC, BE; Sudipta Bhawmik – Qualcomm, USA
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14:20 |
3D-IC Total Yield Assurance
Iris Hirsch, Omri Katz, Ran Kipper – Camtek,IL |
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| 14:45h |
Session 10 - 3D Test Quality and Failure Analysis |
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Testing of TSV-Induced Small Delay Faults for Three-Dimensional Integrated Circuits
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| More Information |
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Further Information
Yervant Zorian
General Chair
Synopsys
700 E. Middlefield Rd.
Mountain View, CA, USA
tel. +1 (650) 584-7120
yervant.zorian@synopsys.com
Erik Jan Marinissen
Program Chair
IMEC
Kapeldreef 75
B-3001 Leuven, Belgium
tel. +32 (0)16 28-8755
erik.jan.marinissen@imec.be
Said Hamdioui
Program Chair
Delft University of Technology
Mekelweg 4
2628CD, Delft, the Netherlands
tel. +31 (0)15 278-3643
s.hamdioui@tudelft.nl
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| Committees |
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General Chair:
Y. Zorian – Synopsys (US)
Program Chairs:
E.J. Marinissen – IMEC (BE)
S. Hamdioui – TU Delft (NL)
Finance Chair:
B. Eklow – Cisco Systems (US)
Publication Chair:
L. Ciganda – Politecnico di Torino (IT)
Publicity Chair:
F. von Trapp – 3DInCites (US)
Web Chair:
G. Jervan – Tallinn Univ. of Techn. (EE)
Arrangements Chair:
J. Potter – Asset Intertech (US)
Program Committee Members:
S. Adham – TSMC (CAN)
V. Agrawal – Auburn Univ. (US)
S. Bhatia – Oasys (US)
C. Bullock – Texas Instruments (US)
K. Chakrabarty – Duke Univ. (US)
S. Chakravarty – LSI (US)
V. Chickermane – Cadence (US)
E. Cormack – DfT Solutions (UK)
A. Crouch – Asset Intertech (US)
J. Foerstel – Altera (US)
S.K. Goel – TSMC (US)
G. Fleeman – Advantest (US)
M.-L. Flottes – LIRMM (FR)
P. Franzon – NC State Univ. (US)
M. Higgins – Analog Devices (IRL)
C.-L. Hsu – ITRI (TW)
S.-Y. Huang – NTHU (TW)
R. Kapur – Synopsys (US)
M. Knox – IBM (US)
M. Laisne – Qualcomm (US)
P. Lebourg – ST Microelectronics (FR)
S. Lecomte – ST-Ericsson (FR)
H.-H. Lee – Georgia Tech (US)
K.H. Lee – GigaLane (KR)
A. Leong – MicroProbe (US)
I. Loi – Universita di Bologna (IT)
M. Loranger – FormFactor (US)
C. Mayor – Presto Engineering (FR)
T. McLaurin – ARM (US)
K. Parker – Agilent Technologies (US)
S. Pateras – Mentor Graphics (US)
B. Patti – Tezzaron Semiconductor (US)
F. Pöhl – Intel (DE)
M. Ricchetti – AMD (US)
D. Rishavy – TEL Test Systems (US)
T. Thärigen – Cascade Microtech (DE)
E. Volkerink – Advantest (US)
Y. Xie – Penn. State Univ. / AMD (US)
Q. Xu – Chinese Univ. Hong Kong (HK) |
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The Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012) is sponsored by the Institute of Electrical and Electronics Engineers
(IEEE) Computer Society's Test Technology Technical Council (TTTC). |
